The expansion of the portable audio market has led to an increase in the complexity of these portable audio devices. In providing users with an influx of new features, these portable devices can provide benefits beyond just simply allowing a user to listen to recorded audio when mobile. Compatibility among the portable audio devices and various components can often be difficult since most audio sources operate at distinctly different sample rates.
Digital asynchronous sample rate converters (“ASRCs”) were manufactured to rectify the disparity between the different sample rates of the audio devices. FIG. 1 illustrates a standard design of a digital ASRC. During operation, ASRC 10 receives an input signal, Din, at an initial sample rate of Fsin. ASRC 10 interpolates Din with interpolator 20 by an interpolation ratio, U, resulting in a high sample rate, U*Fsin of the input signal. Interpolator 20 outputs the interpolated signal to a low pass filter 30. Low pass filter 30 is used to remove any present images that were generated by the interpolation of the input signal. The low pass filter 30 outputs the filtered signal to a decimation filter 40. Decimation filters are primarily used to lower the sampling rate of a given input, and decimation filter 40 can downsample the filtered signal by a determined downsampling rate, D, resulting in an output of the input signal with a sampling rate Fsout according to Equation (i):Fsout=(U/D)*Fsin  (i)
One of the problems that may be raised with existing digital ASRCs is the possibility that the output sampling rate is lower than the input sampling rate, namely Fsout<Fsin. This may occur for a number of reasons, including if the downsampling rate is greater than the interpolation ratio, as demonstrated by equation (i). In instances in which this may occur, some signal in the passband of Fsin folds back as noise into the passband for Fsout. Previous ASRC systems have attempted to correct this issue by increasing the order of the low pass filter. Systems that use this technique increase the order of the low pass filter to provide for a sufficient amount of attenuation for the signal in the passband of Fsin that otherwise would have folded back as noise. The implementation of these systems requires a large amount of area, an increase in die size for the larger low pass filter, and additional logic needed to implement this system, which is not cost effective.
Other previously designed ARSCs have used other techniques to avoid the signal in the passband of Fsin folding back as noise into the Fsout passband. U.S. Pat. No. 6,834,292 (“the '292 patent”) describes a system where the input sampling rate is not directly converted to the output sampling rate. FIG. 2 illustrates an ARSC similar to the system used in the '292 patent. In FIG. 2, instead of outputting Fsout, ASRC 10 outputs a temporary sampling rate. This temporary sampling rate data is represented by S*Fsout, where S is a fixed constant. The temporary sampling rate is output from ASRC 10 to an external decimation filter 50. Decimation filter 50 decimates the temporary sampling data, S*Fsout, by the fixed constant S. This subsequently outputs the real output sampling rate, Fsout. By using a temporary sampling rate output, in instances where Fsin>Fsout, decimation filter 50 provides enough attenuation for the Fsout passband. The system implemented in FIG. 2 does not have to increase the order of the low pass filter or store a large amount of input data. However, this system has a number of significant drawbacks that make it undesirable.
One of the problems is that the system implemented in FIG. 2 and the '292 patent have an ASRC that no longer produces the output sampling rate (Fsout) as its output, but instead outputs S*Fsout. This is significantly larger than the maximum allowable output sample rate for Fsout. Since a determination of the interpolation ratio is based on the maximum allowable output sample rate and a desired bit accuracy, an ASRC that produces S*Fsout as an output would need to increase the interpolation ratio to maintain a desired bit accuracy. An increase in the interpolation ratio would necessitate an increase in the area of the chip, and lead to an increase in the power consumed by the system.
Thus there remains a need in the art for an efficient and cost-effective asynchronous sample rate converter that prevents a signal in the passband of Fsin from folding back as noise into the passband for Fsout, without increasing the order of the low pass filter or the interpolation ratio. There further remains a need in the art for a designed system to decrease area and decrease power consumption during operation.